Bipolar transistors are commonly used in semiconductor devices, especially for high-speed operation and large drive current applications. A double polysilicon bipolar transistor 10 is shown in FIG. 1. The active area for the transistor is isolated by shallow trench isolation regions 12. The collector 13 is a lightly doped region of one conductivity type in epitaxial layer 14, and the base region is formed by doped regions 16 and 18 of the opposite conductivity type. A heavily doped buried layer 15 lies beneath the collector 13 and is doped the conductivity type of the collector. Doped region 16 is called the intrinsic base region because it lies directly between the emitter and collector of the transistor. Region 18, on the other hand, is known as the extrinsic base region. The extrinsic base region 18 provides an area for connecting to the base of the transistor. The base electrode 20 comprises a first doped polysilicon layer. The emitter region 22 is a doped region of the same conductivity type as the collector and is located within the intrinsic base region 16. The emitter electrode 24 is formed with a second doped polysilicon layer. Contact to the buried layer 15 is made by a heavily-doped collector contact implanted region 28. Oxide region 26 and base-emitter spacers 28 insulate the emitter electrode 24 from the base electrode 20.
The design of the collector of a bipolar transistor influences both its breakdown and high-frequency characteristics. In general a thicker, more lightly-doped collector provides a higher collector-emitter breakdown voltage (BVceo), whereas a thinner, more heavily-doped collector reduces base pushout (Kirk effect) and provides a higher cutoff frequency (fT). Much emphasis has been placed on improving fT in the prior art. For example, in Japanese Patent Application No. 63-154721 a recess is etched in the epitaxial layer in which the collector and base are formed to thin the collector layer between the intrinsic base and a buried layer. In another approach, a phosphorus implant beneath the intrinsic base suppresses base pushout and improves fT. See Sugiyama, et al., “A 40 GHz fT Si Bipolar Transistor LSI Technology,” 1989 IEEE International Electron Devices Meeting Technical Digest, 9.1.1. These techniques, however, result in transistors with low BVceo. The Sugiyama paper, for example, reports a BVceo of only 3.3 Volts.
In contrast, the prior art transistor shown in FIG. 2 is designed for high BVceo. The transistor is identical to that of FIG. 1, except that the n+ buried layer is omitted. This, however, increases both the vertical and horizontal components of the collector resistance. High collector resistance can result in the transistor going into saturation at high collector currents, which can induce latchup by injecting holes into the substrate.
The BVceo and fT of a bipolar transistor have traditionally been subject to a performance trade-off. In other words, transistors designed to operate as power devices typically do not perform well in applications requiring small-signal amplification, whereas transistors designed to amplify small signals typically do not perform well in high-power conditions. As a result, the integrated circuit designer is often forced to compromise or trade off the performance of one type of circuit (e.g. input/output) in the integrated circuit against another type of circuit (e.g. small signal amplifier). Therefore, a need exists for structures and methods that allow for transistors designed for both high BVceo and high fT to be formed on the same monolithic integrated circuit. It is also desirable that both types of transistors be formed in a cost-effective manner without added process steps.
In typical double polysilicon bipolar transistors, the emitter junction 22 in FIG. 1 is formed by implantation and subsequent diffusion of a dopant from the polysilicon contact 24. A fraction of the emitter dopant implant is blocked from reaching the polysilicon contacting the single-crystal silicon region by the portion of the polysilicon contact 24 deposited on the vertical surface of the base-emitter spacer 28. Since the average dose of dopant diffusing through the polysilicon-silicon interface along the entire length of the emitter surface is a function of the ratio of the width of the implanted planar fraction of the polysilicon to the width of the non-implanted polysilicon on the vertical surface of the base-emitter spacers, the emitter diffusion profile and average junction depth becomes a function of the lithographically-defined emitter width. This effect is typically most severe for extremely narrow emitters with lithographically-defined widths less than approximately four times the thickness of the polysilicon contact 24. In this case, the gain of the transistor also becomes a function of the emitter width and the transistor is said to suffer from narrow-emitter effects.
In order to achieve a consistent gain for all the transistors used within a circuit, it is desired that this emitter diffusion 22 extend an equal distance into the single-crystalline silicon for all bipolar transistors on a single silicon substrate, independent of the dimensions of the lithographically-defined emitter region. One method of achieving this size independence of the emitter junction and the transistor gain is by forming an “L”-shaped base-emitter spacer that allows the volume of the vertically-deposited emitter polysilicon to reside within the “L” and outside of the region above the active emitter. This situation allows an implanted region to be formed directly above the entire length of the emitter junction. An additional advantage to the use of an “L”-shaped spacer is that the width of the planar portion of polysilicon located directly above the intrinsic emitter region becomes larger for a given patterned emitter size. This increases the area for creating a low-resistance emitter contact and reduces the susceptibility of the contact to being fully or partially blocked by parasitic spacers formed in the emitter contact region during subsequent CMOS source-drain spacer processing steps.
The “L” spacer is typically formed by the low-pressure chemical vapor deposition (LPCVD) of a stack film of oxide/nitride/oxide and a combination of selective wet and dry etching of the layers. However, the dimensions of an “L”-shaped spacer formed by this method are limited by the etching selectivities between the LPCVD oxide, LPCVD nitride, and a previously-formed thermal oxide layer. Typically, an “L”-shaped spacer with a thin enough body to completely contain the vertically-deposited polysilicon cannot be reliably manufactured. A need exists for a fabrication method to form thin-bodied “L”-shaped spacers reliably.